Many electronic devices such as mobile phones and personal digital assistants (PDAs) are operated by battery power supplies and use SRAMs for data memory.
Recently, it has become important to place circuitry into a deep-sleep mode to minimize circuit leakage. Some circuitry may be switched-off completely using series switches, but volatile memory devices, such as SRAM, that need to retain their contents cannot use that technique, since they lose their data if power is completely removed.
Therefore, to reduce the leakage of memory devices during the standby state, it has been proposed to reduce the voltage across the memory cell, as shown in FIG. 1. The problem encountered when doing this is that the reduced voltage across the SRAM cell has to be generated by a low drop-out (LDO) voltage supply, which requires operating current, and dissipated power equivalent to the leakage multiplied by the voltage between the supply voltage and standby voltage.
Alternatively, a passive series regulator can be used which dissipates dissipated power equivalent to the leakage multiplied by the voltage between the supply voltage and standby voltage, and may not produce a very consistent low voltage supply.
Therefore, a need exists to provide a solution, that minimizes power dissipation in SRAMs and other memory types during the sleep state, that eliminates the need for a LDO in sleep mode.
Accordingly, what is needed is an on-chip solution that requires lowest power and permits the entire memory to retain the same voltage supplies.
Therefore, a need exists to overcome the problems with the prior art as discussed above.